Interconnect lines (hereinafter, “interconnects”) are commonly used to carry electricity in microcircuits. While interconnects are often formed of copper, a major reliability concern with copper interconnects is electromigration. Electromigration is the diffusion of copper caused by the gradual movement of copper ions due to the momentum transfer between conducting electrons and diffusing copper atoms. The effect is important in applications where high direct current densities are used, such as in microelectronics and related structures.
The grain structure of copper interconnects can have a profound influence on back end performance metrics such as electromigration performance (due to enhanced atomic mobility at grain boundaries). Thus, conventional processing of copper interconnects typically includes an annealing step used to control the crystal structure of the copper. Typically, the annealing is performed after the copper is deposited and before polishing removes excess copper, that is, the overburden. By annealing the copper within a trench with the overburden present, the overburden is able to facilitate recrystallization and grain growth of the copper such that columnar and “bamboo” grain structures grow. “Bamboo” grains are those that span the trench from the top surface of the copper to the bottom and from side to side with no grain boundary intersecting. Columnar grains span from the top to the bottom. FIG. 1 is a schematic cross-sectional illustration of a semiconductor structure 10 having three copper interconnects 12, 14, and 16 formed within a dielectric material layer 18. A barrier layer 20 is disposed within the trench to prevent or minimize the diffusion of the copper into the dielectric material layer. The wide copper interconnect 12 has a bamboo structure, as shown by grain boundaries 22 and 24. The wide interconnect 14 has columnar grain structures, as shown by grain boundaries 26, 28, and 30. These bamboo and columnar grain structures minimize electromigration effects.
However, as feature sizes of integrated circuits (ICs) decrease below 45 nm node technology, copper interconnects with bamboo and columnar grain structures become difficult to achieve and the practical significance of electromigration in copper interconnects increases. At 45 nm node technology and below, annealing results in “gravel defects” such as those of narrow interconnect 16 of FIG. 1. “Gravel defects” are small, non-columnar grains at the bottom of the trench, as shown by grain boundaries 32, 34, and 36. These grain boundaries form a grain boundary network that can significantly increase electromigration effects. Thus, methods for forming copper interconnects that achieve recrystallization and grain growth of the copper with bamboo and columnar grain structures are preferred.
Accordingly, it is desirable to provide methods for forming copper interconnects that exhibit minimal electromigration effects. In addition, it is desirable to provide methods for forming copper interconnects that utilize force to facilitate the recrystallization and grain growth of the copper into bamboo and columnar crystal structures during annealing. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.